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| APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Product Features Frequency Table n n n n n n n n Supports clock requirements for Mobile Pentium Processor 2 Host and 5 PCI clocks Separate supply pins for mixed (3.3/2.5V) voltage application. <175ps skew among CPU clocks. < 250ps skew among PCI clocks. 48mhz for USB. 28-pin SSOP package for minimum board space. Power management capabilities (R) SEL100/66# CPU PCI 0 66.4 Mhz* 33.3 Mhz 1 99.8 Mhz** 33.2 MHz *Down Spread 1.25% (total); **Down Spread .5% (total) Block Diagram XIN VDDR REF Pin Configuration OSC XOUT CPU_STOP# PCI_STOP# PLL VDDC CPUCLK (0:1) VDDP SEL1066# PWR_DWN# PCI (1:5) PCI_F PLL 48 MHz XIN XOUT VSS PCI_F PCI1 VDDP PCI2 PCI3 VDDP PCI4 PCI5 VSS VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS VDDR REF VDDC CPU0 CPU1 VSS VDD VSS PCI_STOP# CPU_STOP# PWR_DWN# 48M SEL100/66# Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 1 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Pin Description PIN No. 1 Pin Name XIN PWR VDD I/O I TYPE OSC1 Description On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal On-chip reference oscillator output pin. Drives an external parallel resonant crystal. When an externally generated reference signal is used at Xin, this pin is left unconnected Frequency select input pins. See frequency select table on page 1. Clock outputs. CPU frequency table specified on page 1. Free running PCI clock. When PCI_STP# = 0, this clock does NOT stop. 48 MHz fixed clock. PCI bus clocks. See frequency select table on page 1. Buffered outputs of on-chip reference oscillator. When driven to a logic low level, this pin will synchronously stop all PCI clocks (except PCI_F) at a logic low level. When driven to a logic low level, this pin will synchronously stop all CPU clocks at a logic low level. This pin is active low. When asserted low, the device is in shutdown mode. VCO's, Crystal, and outputs are turned off. 3.3 volt power supply for core logic. Ground pins for the device. 2 XOUT VDD O OSC1 15 23, 24 4 16 5, 7, 8, 10, 11 26 19 18 17 13, 21 3, 12, 14, 20, 22, 28 9, 6 25 27 SEL100/66# CPUCLK (0:1) PCI_F 48M PCI(1:5) REF PCI_STOP# CPU_STOP# PWR_DWN# VDD VSS VDDC VDDP VDD48 VDDP VDDR - I O O O O O I I I P P PADI4 BUF1 BUF4 BUF3 BUF4 BUF3 PAD PU PAD PU PAD PU - VDDP VDDC VDDR - P P P - 3.3 Volt power supply pins for PCI (1:5) and PCI_F clock output buffers. 3.3 or 2.5 Volt power supply for CPUCLK (0:1) outputs. 3.3 Volt power supply pins for reference clock output buffers and crystal circuit. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 2 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Power Management Functions All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PCI_STOP# and CPU_STOP# input pins. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within 0.2 mS. The CPU and PCI clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. PWR_DWN# 1 1 1 1 0 CPU_STOP# 0 0 1 1 x (don't care) PCI_STOP# 0 1 0 1 x (don'tcare) CPUCLK LOW LOW RUNNING RUNNING LOW PCICLK LOW RUNNING LOW RUNNING LOW OTHER CLKs RUNNING RUNNING RUNNING RUNNING LOW XTAL & VCOs RUNNING RUNNING RUNNING RUNNING OFF Power Management Timing PCI_F PCI_STOP# PCICLK(1:5) CPU_STOP# CPUCLK(0:1) Power Management Timing Signal CPU_ST0P# PCI_ST0P# Signal State 0 (disabled) 1 (enabled) 0 (disabled) 1 (enabled) Latency No. of rising edges of free running PCICLK (PCIF) 1 1 1 1 NOTES: 1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable goes low/high to the first valid clock comes out of the device. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 3 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Spectrum Spread Clocking Down Spread Amplitude (dB) With Spectrum Spread Without Spectrum Spread Center Frequency (MHz) Spectrum Analysis Maximum Ratings This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout) -0.3V 0.3V -65C to + 150C 0C to +70C 7V Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 4 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Electrical Characteristics Characteristic Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol VIL VIH IIL IIH VOL VOH Ioz Idd Isdd ISC Min 2.0 Typ Max 0.8 -66 5 0.4 10 140 70 Units Vdc Vdc A A Vdc Vdc A mA A mA Conditions - 2.4 25 - All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) CPU = 66.6 MHz, PCI = 33.3 MHz pwr_dwn# (PIN17) = 0 1 output at a time - 30 seconds VDD = VDDP=VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C Switching Characteristics Characteristic Output Duty Cycle CPU to PCI Offset Buffer out Skew All CPU and PCI Buffer Outputs Period Adjacent Cycles Jitter Spectrum 20 dB Bandwidth from Center Symbol tOFF tSKEW P BW J Min 45 1 Typ 50 3 Max 55 4 250 +250 500 Units % ns ps ps KHz Conditions Measured at 1.5V 15 pf Load Measured at 1.5V 15 pf Load Measured at 1.5V - VDD = VDDP =VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 5 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Buffer Characteristics Buffer Characteristics for CPUCLK(0:1) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Dynamic Output Impedance Rise Time Between 0.4 V and 2.0 V Fall Time Between 0.4 V and 2.0 V Symbol IOHmin IOHmax IOLmin IOLmax Zo TR TF Min -40 -74 55 75 10 0.4 0.5 Typ Max 15 1.6 1.6 Units mA mA mA mA Ohms nS nS Conditions Vout = VDD - 0.5V Vout = 1.25V Vout = 0.4V Vout = 0.6V 66 and 100 MHz 20 pF Load 20 pF Load VDD = VDDP= VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C Buffer Characteristics for REF, 48M Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Dynamic Output Impedance Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol IOHmin IOHmax IOLmin IOLmax Zo TR TF Min -13 -30 13 30 18 0.5 0.5 Typ Max 25 2.0 2.0 Units mA mA mA mA Ohms nS nS Conditions Vout = VDD - 0.5V Vout = 1.5V Vout = 0.4V Vout = 1.5V 66 and 100 MHz 20 pF Load 20 pF Load VDD = VDDP= VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C Buffer Characteristics for PCI_F, PCI(1:5) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Symbol IOHmin IOHmax IOLmin Min -18 -44 18 Typ Max Units mA mA mA Conditions Vout = VDD - 0.5V Vout = 1.5V Vout = 0.4V Vout = 1.5V 66 and 100 MHz 30 pF Load 30 pF Load Pull-Down Current Max IOLmax 50 mA Dynamic Output Impedance Zo 14 20 Ohms Rise Time Between 0.4 V and 2.4 V TR 0.5 2.0 nS Fall Time Between 0.4 V and 2.4 V TF 0.5 2.0 nS VDDP= VDDR =3.3V 5%, VDDC = 2.5V 5%,, TA = 0C to +70C Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 6 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Crystal and Reference Oscillator Parameters Characteristic Frequency Tolerance Symbol Fo TC TS TA Mode Pin Capacitance DC Bias Voltage Startup time Load Capacitance Effective Series resonant resistance Power Dissipation Shunt Capacitance X1 and X2 Load OM CP VBIAS Ts CL R1 0.3Vdd Min 12.00 Typ 14.31818 5 Vdd/2 20 0.7Vdd 30 40 Max 16.00 +/-100 +/- 100 5 pF V S pF Ohms Note 1 Units MHz PPM PPM PPM Calibration Note 1 Stability (Ta -10 to +60C) Note 1 Aging (first year @ 25C) Note 1 Parallel Resonant Capacitance of XIN and Xout pins Conditions DL CO CL - -17 0.10 7 mW pF pF Note 1 Internal crystal loading capacitors on each pin (to ground) For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 18.0 pF the total parasitic capacitance would therefore be = 20.0 pF(matching CL) Note 1: It is recommended but not mandatory that a crystal meets these specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 7 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Package Drawing and Dimensions C L E H SYMBOL A A1 D A2 A1 B e A C D E e H a L 0.301 0 0.022 0.005 0.397 0.205 0.006 0.402 0.209 0.0256 BSC 0.307 4 0.030 0.311 8 0.037 7.65 0 0.55 0.009 0.407 0.212 0.13 10.07 5.20 0.15 10.20 5.30 0.65 BSC 7.80 4 0.75 7.90 8 0.95 0.22 10.33 5.38 A2 a 28 Pin SSOP Outline Dimensions INCHES MIN 0.068 0.002 0.066 0.010 NOM 0.073 0.005 0.068 0.012 MAX 0.078 0.008 0.070 0.015 MIN 1.73 0.05 1.68 0.25 MILLIMETERS NOM 1.86 0.13 1.73 0.30 MAX 1.99 0.21 1.78 0.38 B Ordering Information Part Number SG556BYB Note: Package Type 28 PIN SSOP Production Flow Commercial, 0C to +70C The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Cypress SG556BYB Date Code, Lot # Marking: Example: SG556BYB Flow B = Commercial, 0C to + 70C Package Y = SSOP Revision Device Number Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 8 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 9 of 10 APPROVED PRODUCT SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Document Title: SG556 Mobile Pentium(R) Processor Application Clock Generator with SSCG, USB and Power Management Support Document Number: 38-07016 Rev. ECN No. ** 106944 Issue Orig. of Date Change 06/29/01 IKA Description of Change Convert from IMI to Cypress Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07016 Rev. ** 5/17/2001 Page 10 of 10 |
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